Decoding system

ABSTRACT

A decoding system comprising a network including a plurality of signal supply terminals respectively corresponding to individual digits in the form of binary code, a signal source generating electric signals of three different values in response to the most significant digit and each corresponding digit, said electric signals being selectively applied to the corresponding signal supply terminals by means of switching circuits.

United States Patent 91 Murakami et al.

DECODING SYSTEM Inventors: Junzo Murakami, Kawasaki; Shigeo Asakawa, Tokyo; Keiji Takeuchi, Yokohama, all of Japan Tokyo Shibaura Electric Co., Ltd., Kawasaki-shi, Japan Filed: Dec. 16, 1971 Appl. No.: 208,811

Related US. Application Data Continuation of Ser. No. 859,879, Sept. 22, 1969.

Assignee:

Foreign Application Priority Data [451 May 7,1974

[56] References Cited UNITED STATES PATENTS 2,718,634 9/1955 Hansen 340/347 DA 3,223,992 12/1965 Bentley et al. 340/347 .DA R26,076 9/1966 Bentley et al..... 340/347 DA 3,366,804 l/l968 Heaviside 340/347 DA OTHER PUBLICATIONS IBM Technical Disclosure Bulletin, Breedlove, Vol. 3, No. 7, Dec. 1960, pg. 17.

Primary Examiner-Charles Miller Attorney, Agent, or Firm-Flynn & Frishauf [5 7] ABSTRACT A decoding system comprising a network including a plurality of signal supply terminals respectively corresponding to individual digits in the form of binary code, a signal source generating electric signals of three different values in response to the most significant digit and each corresponding digit, said electric signals being selectively applied to the corresponding signal supply terminals by means of switching circuits.

5 Claims, 30 Drawing Figures DECODING NETWORK VOLTAGE DRIVEN LADDER RESISTOR NETWORK CURRENT DRIVEN LADDER RESISTOR NETWORK CURRENT DRIVEN WEIGHTING RESISTOR NETWORK WEIGHTING CURRENT 5 IN UMM e NETWORK mmmm mu.

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SHEET 13 0F 13 DECODING SYSTEM 859,879, filed Sept. 22, 1969.

The present invention relates to a PCM signal decoding system converting a digital signal into a corresponding analogue signal.

Digital-to-analog converting circuits used for decoders in receiving apparatus for PCM communication systems, and used for local decoders in feed-back type coders in transmitting apparatus, include a voltage driven ladder resistor network, a current-driven ladder resistor network, a current-driven weighting resistor network, or a weighting current summing network as shown in FIG. 1.

All of these networks, well known as high-speed decoders, convert digital signals into analogue signals by selectively supplying two different values of voltage or current from the source, namely +E and .Ef or l-l and I, for each bit of the digital signal.

These digital-to-analogue converting networks require very severe restrictions upon the values of their resistors and the voltage or current sources in order to obtain sufficient decoding precision.

Especially in a voice PCM communication system in which digital compressing and expanding or companding is used for improvement of the quantization noise characteristics, there is required an extremely strict decoding precision in the vicinity of the zero level of the analogue voice signals. Thus, when the conventional decoding system is used, the required resistor and 'voltage or current source precision would take an impracticable value as is described hereinafter more in detail.

By way of example, a prior art voltage-driven ladder resistor network as shown in FIG. 2A and in FIG. 2B

will be described. The illustrated network includes voltage sources E E E,, respectively corresponding to different bits of the digital signal. These sources are switched to supply either one of the voltage values +E" and E" by means of switches S S S 8,, S S,, as shown in FIG. 2B. To the voltage sources E E E,, are connected associated resistors each having a resistance value of 2R. These resistors are connected together through resistors having a resistance value of R. To the extreme terminal of the network are connected resistors such that the resultant resistance is 2R.

It is now assumed that in the voltage-driven ladder resistor network shown in FIG. 2A the errors of the parallel arm resistors are respectively 6 8 S,,

and the errors of the series arm resistors are respectively 5,, 6,, and that the voltage sources have no error. The code digital signal is represented by natural binary n-bit digital syrnbol 0 C c,,- with c being the most significant digit and C,,., being the least significant digit.

Switches S, (i= 0, l, n-l are operated in accordance with the values of respective bits C (i O, l,

. 6 n-l whereby l-E or E is selected corre- 0 2 wliei EEK 2G, withi dj fffjqfihsfthe voltage l'lout at output terminal P is expressed as out 2n+1 Where A, is the error (or deviation) of the output voltage from the theoretical value. Denoting the maximum absolutevalues of resistance errors 8 '8 15 and 8 6 8,,.,' by 8,, the error A, results in As the precision in the vicinity of O-level of the analogue signal is particularly important for digital companding', the errors in this vicinity will be considered. 1

analo ue And that corresponding to digital signal (01 l l l is V The difference between the two analogue value is known from equations (4) and (5),

As the ideal difference is equal to the unit step value E/Z the error Ais A 2"A 2" A =6, i It-2 (8) Thugif tlie 55mins error] Al ifib heldwithin Substitution of equation (3) into equation (7) gives ill; of thejunit step in the neighborhood of the-O-level of the analogue signal, equation (8) restricts the maximum error 8,, of the resistors to' ll BX 2 k-2"'* k=1 where 1/3 is the error allowance.

By way of example, 8,, of an" 11-bit natural binary code decoder having a error allowance of 1/10, from equation 9 2.45- l0 0.00245 percent Analogously, denoting the maximum error of resistors constituting a current-driven ladder resistor network by 8,,

In either case it is practically impossible to provide resistors meeting the above precision requirement. The impossibility becomes further evident from the consideration of changes in resistance with temperature and time. Furthermore, the residual resistance of the switching circuits for the voltage sources and the stability of the reference voltage dictate an even higher degree of precision than the values given by equations (l)and(ll).

These facts also substantially may be applied to other decoding circuits-or networks such as a current-driven weighting resistor network.

The above disadvantages inherent to the conventional digital-to-analogue converting systems are'found to stem chiefly from'selectively supplying the network with two voltage or current values depending upon the values C,.of individual bits of the digital. signal.

The object of thepresent invention is to overcome the foregoing disadvantages by the provision of a decoding system comprising a network including a plurality of signal supply terminals respectively. corresponding to individual digits in the form of binary code, a signal-source generating electric signals of three different values, and switching circuits selectively providing one 1 of said electric signals of three different values in response to the most significant digit signal, each corresponding to'each digit, to the corresponding signal supply terminals.

This invention can be more fully understood from the following detailed description when taken' in, conduction with the accompanying drawings, in which:

FIG. 1 illustrates conventional digital-to-analogue converting networks;

FIGS. 2A and 2B illustrate the principlesof the operation of the conventional current-drivenladder resistor network;

FIGS. 3A and 3B illustrate the principles of the operation of a digital-to-analogue converting network according to the present invention;

FIGS. 4A to 4C show binary charts analyzing the digital compression and expansion;

FIG. 5 is a plot for the decoding characteristic of the network shown in FIGS. 3A and 3B; 1

FIG. 6 is a circuit diagram showing another embodiment of the digital-to-analogue converting network according to the invention;

FIGS. 7 and 8 are plots for the decoding characteristic of the network shown in FIG. 5;

FIG. 9 is a circuit diagram showing a still another embodiment of the digital-to-analogue converting network according to the invention;

FIG. 10 is a plot for the decoding characteristic of the network shown in FIG. 9; and

' FIGS. 11 to 26 are circuit diagrams showing various embodiments of the unit circuit supplying voltages or 4 the principle that three different values of voltage such as +E, 0.and E as shown in FIG. 3B or those of current such as +1, 0 and -I are available corresponding to the values of each bit C, and C of the digital signal. The outstanding advantage of the decoding system according to the invention will become more apparent from the following description. Throughout this specification E represents voltage and 1 represents current. However, in the claims the term E is used to denote an electrical signal value of either voltage or current.

It is now assumed that the control of each switch for a voltage-driven ladder resistor network conforms to the logical relations according to the invention, that is, for a digital signal in the form of natural binary code (C0 l C2 n-i) i. when C Oand C 0, E,=E,

ii. when C l and C; l, E; E,

when'C l C; 0, E5 0,

iv. when C O and C l, E] O. wherej= l, 2,. n-l.

Then, the j-th voltage E, as shown in FIG. 3A is I 1 0 (COCJ C0CJ)E I Thus, the output voltageEout at terminal P is'expressed as and wherej= l, 2,. nl.

The analogue signal outputs corresponding to natural binary signals (100 0O) and (Oll ll) are obtained by equation (l4) as follows.

(lO0...0O)- =(Oll ll)= O H .99. IL llIE'PSZ.

As is seen from equation (l5), these digital signals are independent of the precision of the resistors.

, becomes Also, the analogue output corresponding to digital signal Ol which is one step above digital signal (I00 00). is given as i I (100 01 (E/2 "")(l A,,

*EPlBEE Similarly, the analogue output corresponding to digital signal (01 l 10) which is one step below digital signal(0ll...ll)is 0. a a .=1 +E Art-o ana o s- I As is apparent from equations (1 6) and l7), the absolute value of the relative error A becomes Thus, if the absolute errorl Al is to be held within 1/8 of the unit step in the neighbourhood of O-level of the analogue signal, the maximum errorS of the resistors a, S l/nB where 1/8 is the error allowance.

By way of example, for n ll (-n-bit digital signal) and(l/B)=(l/l0),

a, s 9.1 x 10- =0.91 percent (20 is obtained.

Under the same conditions the maximum error (8),

6, g 1.3 X l =O.l3 percent Setting of the error within these ranges may be easily realized with ordinary resistors. The described decoding system is particularly effective for the decoding of digital signals containing a great quantity of information to corresponding analogue signals. It may also be applied to current-driven weighting resistor networks and weighting current summing networks in addition to the foregoing voltage-or current-driven ladder resistor networks. I

Prior to describing detailed embodiments of the decodingsystem according to the principles of this invention, an explanation of digital companding is first given as it is carried out in the preceding stage of the decoding network for the purpose of improving the quantization noise characteristics. The case of 7-bit-binarycoding of a voice signal is now considered. This is per-' formed by l l-bit-linear-binary-coding of the analogue signal by the compression of 11- digits into 7 digits by a logical'procedure. The compression is accomplished by omitting lower digits of the digital signal as the analogue input level increases. FIG. 4A represents digital pander, where they are converted to l 1-bit digital signals. The lower bits in each segment which have beem omitted by the compressor are indefinite at the output of the expandenBy way of example, when (d d d d )=(l0lllOl), from b d 1 and d d d 011 (segment IV), there is determined where (12 b, 12 is an expanded digital signal. However, digits 1),, and b are not determined, for the two digits in segment IV have been omitted by the compressor. Accordingly, it is necessary to select any one signals as the input to the digital compressor in the form ofa folded binary code. The most significant digit 12 represents the polarity of the analogue input value, with l indicating positive and 0 indicating negative. b, or the other digits are symmetrical with respect to the zero or center level of the analogue signal. Therefore the chart of FIG. 4A covers only b l or the positive region which is divided into segments I, II, VIII which are arranged in the order of analogue input levels nearer to O-Ievel; segment l consists of 2 binary codes from (10000000000) to (100000001 1 l segment II consists of 2 binary codes, and segment VIII consists of 2 binary codes.

For the purpose of compressing the l 1-bit digital signals in FIG. 4A into 7-bit digital signals, 3-bits of each segment above the omitted bits shall be made effective. Segments I and II are not subject to the bit omission, for

segment III the least significant bit is omitted, and the As the probability density of voice level decreases with increasing level, it has been proved that the quantization noise characteristic may be improved by more finely quantizing at the low level where the probability density is high.

The resultant outputs of the digital compressor are 7-bit'signals as shown in FIG. 48, where the most significant bit d remains equal to b of the signals before compression, the following successive three bits d to d indicate the segment to which the signal belongs; that is (000) for segment I, (001) for segment II, (010) for segment 11], and (1 11) for segment VIII, and the remaining three bits d, to d become effective bits in each segment. Thus outputs (d d d include 2 binary codes in each segment.

The regeneration of an analogue signal from the compressed code is performed as follows. First the 7-bit digital signals are introduced into the digital exin addition to switches S, (j l, 2,

of(00) (01) (10) and (11) for b b To expand the digital signal with a minimum of error a value nearest to the center of the omitted level range is taken. Thus,

and the expanded digital output signal is (b b b b, (1000110110). 4

Selecting the value nearest to the center of the omitted level range for each segment, the expanded digital signal as shown in FIG. 4C becomes the input signal to the decoder.

The relation between the folded binary code (b 'b,

. b, b,,.,) and the natural binary code (C C, C, C,, is expressed as As is seen from the equation (22) there are certain relations between both of the binary coding systems, a selected coding system and can be converted to the other, if necessary, by suitable conversion logical circuits.

Thus, the following description is mainly concerned with the folded binary codes having a symmetrical characteristic. Consideration is first given to the decoding characteristic of the output from the voltage-driven ladder resistor circuit shown in FIG. 3 in the vicinity of O-level. It is assumed that the digital companding is carried out in accordance with the charts of FIGS. 4A to 4C. FIG. 5 shows the digital signal input taken along the x-axis and the analogue signal output taken along the y-axis for a portion of segment I. The analogue signal output for the folded binary digital input signal is theoretically given from equations (14) and (22) as .EEQLQ'JU 2 i (23 wherej=l,2,...,n.

For the analogue signal outputs corresponding to digital signal inputs (I00 00) and (011 11) there is obtained:

(l0O...O0)=(0ll 1l)=0 analo ue analogue The circuit shown in FIG. 3 having the decoding characteristic shown in FIG. 5 is, of course, sufficient for practical use, in spite of being connected in common at the analogue signal output corresponding to the above digital signals.

An improvement of the circuit shown in FIG. 3 is shown in FIG. 6. It includes a separate switch S, controlled by the values of the most significant digit in, n l) which tions.

are controlled in the same manneras the switches in the circuit of FIG. 3. I The control of switch 8,, satisfies the logic conditions that the output of switch S is ,+E for 12 land E for b O v (24) Addition of a supplementary term derived from conditions (24) substituted into equation (23) gives 11-1 I E ..E.t..=. 2 z9.. 2 ;+Q.1L; 25

The decoding characteristic of the circuit shown in FIG. 6 and represented by equation (25) is shown in FIG. 7 where the x-axis is also taken for the digital signal input and the y-axis is taken for the analogue signal output. FIG. also shows only a portion of the decoding characteristic. The decoding characteristic for segments l toIV is shown in FIG. 8. This characteristic is not only peculiar to digital companding, but is also applicable for other well known companding systems I The folded types of companding systems tend to gen- .erate third-order distortions (non-linear distortion). .Withthecircuit shown in FIG. 6 only on the boundary between segments II and III is there a discrepancy of mean values as-is seen from the decoding characteristic of FIG. '8, which is the cause of the third-order distor- Unit step forsegments I and II is a, 0 E/ 2i0 U Unit step for segment III is 0 2U 'Unit step for segment IV is 0., 2 U Unit step for segment V is 0' 2 U 1 Unit step for segment VIII is 0 2U (26) At the boundary between segments III and IV the step value y is obtained from equation (26) controlled by the logical equation (24). The most prefverable embodiment of the decoder which improves the linearity of this decoding system is shown in FIG. 9. A

major difference of the circuit shown in FIG. 9 from the same manner a switches Sj in the circuits of FIGS. 3

and 6. Switch Sn on the other hand, is controlled according to the following logical conditions:

i. When b l and b, b 1);, 17., b b 0, the voltage value is E. ii. when b0 and b1 b2 b3 b417 b6 0, the voltage value is E. r iii. For the other cases the voltage value is 0. 29 By controlling switch Sn such that equation (29) is satisfied, for segments-I and II of the digital input signalsthe output signal is corrected by E/2" V/2 in the positive direction when the most significant digit is l and by 14/2 in the negative direction when the most significant digit is 0. Therefore, the complete linear relation among the mean values of the decoding characteristic as shown in FIG. 10 is obtained,- and the third In this circuit resistor 20 inserted between terminal 9 and ground potential is the equivalent resistance of the ladder resistor network viewed from terminal '9.

Terminal 9 is connected to common line'l0 which is'in turn connected to grounded current source 5. Current source 5 supplies one of the two currents J, and J which have some constant magnitude but have opposite polarities. To common line 10 is also connected the anodes of diodes 1 and 3 and the cathodes of diodes 2 and 4. Upon the cathode of diode l is impressed voltage V and upon the anode of diode 2 is impressed voltage V The cathode of diode 3 and the anode of diode 4'are connected to terminal 12 through the'switching elements 6- and 7 respectively and upon terminal'l2 is impressed voltage V Switching elements 6 and 7 are operated in opposite directions to each other with the control signal fed to terminal 8.

It is now assumed that voltages V V and V are the following relation,

The operation of the switching'circuit will now be de- Thus terminal 9 is connected to the terminal 12 with voltage V Current J to be introduced into current source 5 flows from V through diode 2, and upon terminal 9 is impressed voltage V Next it is assumed that switching element'6 is turned off and then switching element 7 is turned on. Current J from current source 5 flows through diode l, and then terminal 9 has volt ageV j m i Current J to be'introduced' into current source 5 flows from terminal 12 throughswitching element 7 anddiode 4,since V V At this time the terminal 9 has voltage V j v v Thus, it is possible to supply one of the three voltages V V and V by controlling the control-signal fedto terminal 8 and the direction of current fed to current source 5. I FIG. 12 illustrates a more detailed arrangement of the switching circuit showing in FIG. 1 l, with diodes '12 and 18 constituting switching element 6 and diodes l3 and 19 constituting switching element 7. To-terminal 11 is supplied the signal of the most significant digit C and to terminal 14 is supplied the signal of each digit C,, is the natural binary code. Signal C is fed'to diodes 18 and 19 through the resistor of high resistances l6 and 17 respectively. Similarly, signal C, is supplied through high'resistan'ce '15 to common line 10 and may be regarded to be the constant current source.

It is considered that in this circuit voltages +V" and *V" are impressedv in' correspondence with l and. O of signals C and C and that voltage +E corresponds to V, in the circuit of FIG. 11, voltage -E corresponds to V and groundpotential corre sponds to V Voltages V and E are related as i. When C 0 V) and C,= 0 V), current flows from ground through diodes 12 and 18 and resistor 16 to terminal 11 as well as from E) through diode 2 and resistor to terminal 14. Thus, terminal 9 is supplied with voltage E).

ii. When C l V) and C,= l V) current flows from the terminal 11 through resistor 17 and diodes 19 and 13 to ground as well as from terminal 14 through resistor 15 and diode 1 to +-E). Thus, terminal 9 is supplied with voltage E).

iii. When C O V) and C, l V), current flows from terminal 14 through resistor 15, diodes 3 and 18 and resistor 16 as well as from ground through diodes 12 and 18 and resistor 16. Thus, terminal 9 is at ground potential.

iv. When C1, l V) and C 0 V), current flows from terminal 11 through resistor 17, diodes l9 and 4 and resistor 15 as well as from terminal 11 through resistor 17, diodes l9 and 13 to-ground. Thus, terminal 9 is at ground potential.

As is apparent from the foregoing, this circuit satisfies equation (13).

The circuit shown in FIG. 13 is obtained by eliminating diodes 18 and 19 from the circuit shown in FIG. 12,

and operates similarly to the circuit of FIG. 12.

For either of the above switching circuits it is desirable that current through diodes 12 and 3 is substantially equal to current through diodes 13 and 4.

The circuits shown in FIGS. 14 and 15 use diode bridge gates consisting of four diodes.

In the circuit shown in FIG. 14 the bridge gate consists of diodes 21, 22, 23 and 24. The anodes of diodes 21 and 22 are connected through resistor 15a to terminal 14a, cathodes of diodes 23 and 24 are connected through resistor 15b to terminal 14b, the cathode of diode 22 and the anode of diode 24 are connected to terminal 9 which is connected through resistor 25 to terminal 11 to which is impressed the voltage V, or V corresponding to the most significant digit b of l or 0" respectively, and through resistor to the ground, and through diodes 1 and 2 to +E and E, the cathode of diode 21 and the anode of diode 23 are grounded respectively. The cathode of diode 2 and the anode of diode l are connected to terminal 9. To input where (B b b,, IS the foldedbinary code.

If the diodes have ideal switching characteristics of impedance zero or infinity in this circuit, then terminal 9 is at 0 potential for b, is equal to 0". However, as the actual diodes have finite impedance variable with current, this circuit does not operate an ideal voltage source and terminal 9 can not be supplied with exact voltage of +E, E or O. This imperfection causes decoding errors. U V

The circuit shown in FIG. 15 is intended to improve the foregoing disadvantage and comprises a diode bridge gate consisting of diodes 26, 27, 28 and 29 and inserted between resistor and input terminal 11, with the connection between diodes 26 and 28 connected through resistor 30 to input terminal 14a and the connection between 27 and 29 connected through resistor 31 to input terminal 14b.

Terminal 1! is controlled such that it is for instance,

.at +6 volts when b 1 and at 6 volts when 12., 0.

Terminals 14a and 14b are controlled such that they are respectively at 9 volts and +9 volts for by l and at +9 volts and 9 volts for b 0. When b 0, the diode bridge gate consisting of diodes 26, 27, 28 and 29 is made off and the effect of 11,, is removed.

It is of course to be understood that known gate circuits may be used for each of the diode bridge gates so long as they perform the foregoing operation.

An embodiment of the current-driven type ladder resistor network is now described. The decoder output voltage from the current-driven type ladder resistor network with respect to folded binary code signal (b b b b,, and natural binary code signal (C C Q -.i e stv s s d as (C C -df) X i Therefore the unit circuit shall supply a current I,- of the following equation;

FIG. 16 shows a diode bridge circuit used as the current switch, where the value of a grounded resistor 20 is equal to the equivalent resistance of the ladder resis tor network as viewed from terminal 9. To the free end of resistor 20 is connected the anode of diode 32, and the cathode of diode 33. The anode of diode 33 is connected with the anode of diodes 34 and 35, and through resistor 36 to a constant voltage +E. The cathode of diode 34 is connected with the anodeof diode 37 and the input terminal 11 to which the most significant digit 12 of the folded binary code is supplied.

Further, the cathode of diode 37 is connected with the cathodes of diodes 32 and 38 and through resistor 39 to a constant voltage -E.

The cathode of diode 35 and the anode of diode 38 are respectively connected with the terminals 14a and 14b to which corresponding digit b, of the folded binary code is supplied with opposite'polarities.

The above described circuit is a switching circuit supplying currents +1 or -I when h, l and no current whenb, 0 to the current-driven type network. The magnitude of current 1 depends on-the value of the voltage source and resistors 36 and 39. Terminal 11 is controlled by the most significant digit alternatively b, so as to be for instance, +2 volts when b l and 2 volts when b 0. Terminals 14a and 14b are controlled by each digit b, so as to be, for instance, +2 volts and 2 volts respectively, when 12, l, and -2 volts and +2 volts when b, 0. It is also assumed that, E is equal to 12 volts and silicon diodes with a forward voltage drop of about 0.7 volts are used here. First, when h b, 1, terminal 14a and 11 are at +2 volts, and terminal 14b at 2 volts. Diodes 33 and 37 are forward-biased with little resistance, while diodes 32, 34, 35 and 38 are backward-biased with very high resistance. The voltage at point D is 1.3 volts and that at point C is 1.2 volts because of forward voltage drop across the diodes provided that terminal 9 is at 0.5 volts owing to the output current. Now a current flows from terminal 11 to the voltage source E and another from the voltage source +E to terminal 9, as the output current of the switching circuit. Second, when b O and by l, diodes 33, 34, 37 and 38 are turned off and current 'I is supplied from 12 volts terminal through resistor 39 and diode 32 to resistor 20. Third, when b 1 and by 0, and b O and b, 0 both 33 and 32 are turned off, so that there flows no current through resistor 20. The voltage furnished to terminals 11, 14a and 14b may be desirably selected that the foregoing operation is ensured. Cur rent I supplied to the ladder network is determined by the magnitude of the required analogue output, thus determine voltage and resistors 36 and 39. When very high resistance is required for resistor 36 and 39, the voltage sources and resistors may, of course, be replaced by constant current circuits consisting of transistors and the like.

The circuit shown in FIG. 17 has AND gate 40 and OR gate 41 driven by natural binary code signal C and C]. The output of the gates are supplied to respective level shifters 42 and 43. By way of example, level shifter 42 shifts the output level of AND gate 40 to +6 volts for l and to +4 volts for 0", while level shifter 43 shifts the output level of OR gate to 4 volts for l and'to 6 volts for 0". The level-shifted signal is supplied through diodes 44 and 45 to the emitters ofp-n-p transistors 46 and n-p-n transistor 47 for switching. Resistors 48 and 49 are durrent-limiting resistors across which are applied voltages E, and -E,. To the bases of transistors 46 and '47 are applied constant voltages +E and E whose values are, for instance, IE, I 20 volts and IE I volts.

The collectors of transistors 46 and 47 are connected together to terminal 50 which is in turn connected to grounded resistor 51 which is the equivalent resistance of the ladder circuit as viewed from terminal 50,

The operation of this switching circuit with the signals fed to the input terminals 52 and 53 is now described.

i. When (C C C is natural binary code signal and C C, 0, both of the outputs of AND gate 40 and OR gate 41 are 0", so that the output voltage of level shifter 42 is +4 volts and the output voltage of level shifter 43 is 6 volts. As a result diode 44 is turned on. The emitter voltage for transistor 46 is 4.7 volts because of forwardvoltage drop of the diode. As the base voltage for transistor 46 is 5 volts or 0.3 volts higher than the emitter voltage, transistor 46 is turned off. With a forward voltage drop from the base to the emitter of transistor 47 amounting to'0.7 volts (for silicon transistor) the emitter voltage is -5.7 volts, so that transistor 47 is turned on and diode 45 is turned off,

causing current to flow from-ground through resistor 51, transistor 47 and resistor 49. This current is defined as the negative current --I.

ii. When C .='C, 1, outputs from both AND gate 40 and OR gate 41 are I, so that the output voltage of level shifter 42 is +6 volts and the output voltage of level shifter 43 is -4 volts. As a result, diode 44 is turned off and the emitter voltage for transistor 46 is +5.7 volts. Thus, transistor 46 is turned on, and current flows through transistor 48, transistor 46 and resistorSl. This current is a positive current +1. On the other hand, diode 45 is turned on to provide 4.7 volts for the emitter of transistor 47 so as to turn it off.

iii. When C e C output from AND gate 40 is 0", so that transistor 46 is turned off as in the above case (i). On the other hand,output from OR gate 41 is I so that transistor 47 is turned off as in the above case (ii).

In the switching circuit shown in FIG. 18, the level shifters and switching diodes of the switching circuit shown in FIG. 17 are operated by means of voltage regulator diodes, for instance, Zener diodes 54 and 55.

The circuit shown in FIG. 19 is a modification of the switching circuit shown in FIG. 17. In this embodiment,

' between terminal 52 andthe emitter of transistor 46 is inserted a series circuit of level shifter 56 and diode 60, and between terminal 52 and the emitter of transistor 47 is inserted a series circuit of level shifter 58 and diode 62. Similarly, between terminal 53 and the emitter of transistor 46 is connected a series circuit of level shifter 57 and diode 61, and between terminal 53 and the emitter of transistor 47 is inserted a series circuit of level shifter 59 and diode 63. In this'circuit, the switching of AND gate is made by diodes 60 and 61, and the switching of OR gate is made by diodes 62 and 63.

In the circuit shown in FIG. 20 the level shifters and switching diodes in the switching circuit shown in FIG. 19 are operated'by means of voltage regulator diodes, for instance, Zener diodes 64, 65, 66' and 67. l

. The switching circuit shown in FIG. 21 replaces diodes 60 to 63 in the circuit shown in FIG. 19 with p-n-p transistors 68 and 69 and n-p-n transistors 70 and 71, with +E impressed upon the collector of transistors 68 and 69 and E impressed upon the collector of transistors 70 and 71. For the operation of this circuit there is preset a relation nection circuit consisting of respective pairs of transistors 72, 73 and 74, 75. In this circuit, there is obtained a high impedance when the current source side islooked from current supply terminal 50, thus reducing the effects upon the ladder network ,to the advantage.

The circuit shown in FIG. 23 is another embodiment of the switching circuit for the current-driven type ladder network.

In this circuit, the most significant digit of folded binary code b is fed to terminal 52 and between terminal 52 and the emitters of p-n-p transistor 46 and np-ri transistor 47 are inserted level shifters 42 and 43 and diodes 44 and 45., The collectors-of p-n-p and n-p-n transistors 46 and 47 are jointly connected to gate 76, which is controlled by the respective digit of folded binary code 12, so as to be turned on when digit b, is 1". The emitters of transistors 46 and 47 are connected to respective current limiting resistors 48 and 49, and 

1. A decoding system adapted for use in a non-linear companding voice PCM communication system for decoding a digital signal composed of a plurality of digits into an analogue voice signal, comprising: a netWork including a plurality of signal supply terminals, each corresponding to respective digits of the digital signal being decoded; an output terminal; and means coupling said signal supply terminals to said output terminal; a source of d.c. signals of three different values, +E,0 and -E; a plurality of single stage switching circuits each corresponding to a respective signal supply terminal, single stage switching circuit including means responsive to signals representing the states of the most significant digit and another digit of said digital signal for selectively supplying one of said d.c. signals of three different values from said signal to said respective signal supply terminals; and a further switching circuit including means responsive to a signal representing the state of the most significant digit of said digital signal for supplying one of said d.c. signals of three different values from said signal source to a predetermined signal supply terminal to generate an analogue signal corresponding to said digital signal at said output terminal; each of said switching circuits including a bridge circuit comprised of a plurality of diodes (21-24) connected in a bridge configuration, first and second resistors (15a, 15b) connected at one end to the respective common electrode junctions of pairs of said bridge diodes and at the other end to respective first and second terminals (14a, 14b) supplied with digit signals (bj and bj, respectively). means coupling another junction of said bridge diodes (21, 23) to ground, a third resistor (25) connected at one end to the remaining junction of said bridge diodes (22, 24) and at the other end to a digit terminal (11) supplied with the most significant digit signal (b0), a common line connected between said remaining junction of said bridge diodes (22, 24) and the signal supply terminal (9), a first diode (2) having its cathode connected to said common line and its anode supplied with signal -E, and a second diode (1) having its anode connected to said common line and its cathode supplied with signal +E.
 2. A decoding system according to claim 1 comprising: a second bridge circuit including a plurality of diodes (26 - 29) connected between said third resistor (25) and said digit terminal (11), a fourth resistor (30) connected between a common electrode junction of said diodes (26, 28) of said second bridge circuit and said first terminal (14a), and a fifth resistor (31) connected between the other common electrode junction of said diodes (27, 29) of said second bridge circuit and said second terminal (14b).
 3. A decoding system according to claim 1 wherein said further switching circuit further includes means responsive to a signal representing the state of the predetermined ones of said digital signal for supplying one of said D.C. signals of three different values from said signal source to at least one of said signal supply terminals, to thereby generate an analogue signal corresponding to said digital signal at said output terminal and eliminating third order distortion in the decoding of said digital signal.
 4. A decoding system according to claim 1 wherein said network comprises a voltage-driven ladder resistor network.
 5. A decoding system for decoding a digital signal composed of a plurality of digits into an analogue signal, comprising: a source of first and second and third voltages (V1, V2 and V3); a voltage driven ladder resistor type network having a plurality of signal supply terminals; and a plurality of switching circuits is respectively connected to individual signal supply terminals and responsive to said digits of said digital signal for selectively supplying said signal supply terminals with three different values of voltage depending upon the digital signal, said switching circuits each including a common line (10) connected to the coRresponding one of said signal supply terminals, a current source (5) connected to said common line (10) and supplying positive or negative current in accordance with said digital signal a first diode (1) whose anode is connected to said common line (10) and whose cathode is impressed with said first voltage (V1), a second diode (2) whose cathode is connected to said common line (10) and whose anode is impressed with said second voltage (V2), a third diode (3) whose anode is connected to said common line (10), a fourth diode (4) whose cathode is connected to said common line (10), a first switching element (6) controlled by said digital signal and having one terminal thereof connected to the cathode of said third diode (3) and the other terminal thereof impressed with said third voltage (V3), and a second switching element (7) performing an opposite action to said first switching circuit (6) and having one terminal thereof connected to the anode of said fourth diode (4) and the other terminal thereof impressed with said third voltage (V3), wherein said first, second and third voltages (V1, V2 and V3) have a relation to each other as follows: V1 > V3 > V2. 